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HD74LV161A
Synchronous 4-bit Binary Counter (Direct Clear)
REJ03D0319-0400Z (Previous ADE-205-264B (Z)) Rev.4.00 Jun. 04, 2004
Description
The HD74LV161A is 4-bit binary counters. All flip flops are clocked simultaneously on the low to high to transition (positive edge) of the clock input waveform. These counters may be preset using the load input. Presetting of all four flip flops is synchronous to the rising edge of clock. When load is held low counting is disabled and the data on the A, B, C and D inputs is loaded into the counter on the rising edge clock. If the load input is taken high before the positive edge of clock, the count operation will be unaffected. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life.
Features
* * * * * * * VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25C) Output current 6 mA (@VCC = 3.0 V to 3.6 V), 12 mA (@VCC = 4.5 V to 5.5 V) Ordering Information
Package Type SOP-16 pin(JEITA) SOP-16 pin(JEDEC) TSSOP-16 pin Package Code FP-16DAV FP-16DNV TTP-16DAV Package Abbreviation FP RP T Taping Abbreviation (Quantity) EL (2,000 pcs/reel) EL (2,500 pcs/reel) ELL (2,000 pcs/reel)
Part Name HD74LV161AFPEL HD74LV161ARPEL HD74LV161ATELL
Note: Please consult the sales office for the above package availability.
Rev.4.00 Jun. 04, 2004 page 1 of 15
HD74LV161A
Function Table
Inputs CLR L H H H H H LOAD X L H H H X ENP X X X L H X ENT X X L X H X CLK X Outputs QA L A No change No change Count up No change QB L B QC L C QD L D
Note: H: High level L: Low level X: Immaterial : Low to high transition : High to low transition A, B, C, D: Data input Carry = ENT * QA * QB * QC * QD
Pin Arrangement
CLR 1 CK 2 A3 B4 C5 D6 ENP 7 GND 8
16 VCC 15 CARRY OUTPUT 14 QA 13 QB 12 QC 11 QD 10 ENT 9 LOAD
(Top view)
Rev.4.00 Jun. 04, 2004 page 2 of 15
HD74LV161A
Absolute Maximum Ratings
Item Supply voltage range Input voltage range*1 Output voltage range*1, 2 Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation at Ta = 25C (in still air)*3 Storage temperature Symbol VCC VI VO IIK IOK IO ICC or IGND PT Tstg Ratings -0.5 to 7.0 -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to 7.0 -20 50 25 50 785 500 -65 to 150 Unit V V V mA mA mA mA mW C Conditions H or L Output: H or L VCC: OFF VI < 0 VO < 0 or VO > VCC VO = 0 to VCC
SOP TSSOP
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150C.
Recommended Operating Conditions
Item Supply voltage range Input voltage range Output voltage range Output current Symbol VCC VI VO IOH Min 2.0 0 0 -- -- -- -- -- -- -- -- 0 0 0 -40 Max 5.5 5.5 VCC -50 -2 -6 -12 50 2 6 12 200 100 20 85 Unit V V V A mA Conditions
IOL
A mA
Input transition rise or fall rate
t /v
ns/V
VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V
Operating free-air temperature
Ta
C
Note: Unused or floating inputs must be held high or low.
Rev.4.00 Jun. 04, 2004 page 3 of 15
HD74LV161A
Logic Diagram
CLK CLR LOAD
Enable P T A
DQ CK
CLR
DQ CK
CLR
Output QA
Q
Output QB
Q
B
DQ
Output QC
Data Inputs
CK
CLR
Q
C
DQ CK
CLR
Output QD
Q
D
Carry Output
Rev.4.00 Jun. 04, 2004 page 4 of 15
HD74LV161A
Timing Diagram
CLR LOAD A Data Inputs B C D CLK ENP ENT QA Out puts QB QC QD Carry
12 13 14 15 0 1 2
Count Clear Preset (Load)
Inhibit
Rev.4.00 Jun. 04, 2004 page 5 of 15
HD74LV161A
DC Electrical Characteristics
Ta = -40 to 85C Item Input voltage Symbol VIH VCC (V)* 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Min to Max 2.3 3.0 4.5 Min to Max 2.3 3.0 4.5 0 to 5.5 5.5 0 3.3 Min 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 -- -- -- -- VCC - 0.1 2.0 2.48 3.8 -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.7 Max -- -- -- -- 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 -- -- -- -- 0.1 0.4 0.44 0.55 1 20 5 -- Unit V Test Conditions
VIL
Output voltage
VOH
V
VOL
Input current Quiescent supply current Output leakage current Input capacitance
IIN ICC IOFF CIN
A A A pF
IOL = -50 A IOL = -2 mA IOL = -6 mA IOL = -12 mA IOL = 50 A IOL = 2 mA IOL = 6 mA IOL = 12 mA VIN = 5.5 V or GND VIN = VCC or GND, IO = 0 VI or VO = 0 V to 5.5 V VI = VCC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Rev.4.00 Jun. 04, 2004 page 6 of 15
HD74LV161A
Switching Characteristics
VCC = 2.5 0.2 V Ta = 25C Item Maximum clock frequency Propagation delay time Symbol fmax tPLH/tPHL tPLH/tPHL Count mode tPLH/tPHL Load mode tPLH/tPHL tPHL tPHL Setup time tsu Min 50 30 -- -- -- -- -- -- -- -- -- -- -- -- 7.5 10.0 9.5 4.5 Hold time Pulse width th tw 1.5 7.0 7.0 Typ 90 60 11.1 14.3 11.5 14.7 13.8 17.0 10.3 14.0 11.7 14.7 11.2 14.4 -- -- -- -- -- -- -- Max -- -- 16.2 19.2 17.0 20.0 20.6 23.6 15.7 18.7 17.0 20.0 16.6 19.6 -- -- -- -- -- -- -- Ta = -40 to 85C Min 40 25 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 8.5 11.5 11.0 4.5 1.5 7.0 7.0 Max -- -- 19.5 22.5 20.5 23.5 24.5 27.5 19.0 22.0 20.5 23.5 20.0 23.0 -- -- -- -- -- -- -- ns ns Unit MHz ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CLK CLK CLK ENT CLR CLR Q Carry Carry Carry Q Carry FROM (Input) TO (Output)
ns
Data before CLK LOAD before CLK ENT, ENP before CLK CLR inactive before CLK CLK H or L CLR L
Rev.4.00 Jun. 04, 2004 page 7 of 15
HD74LV161A
Switching Characteristics (cont)
VCC = 3.3 0.3 V Ta = 25C Item Maximum clock frequency Propagation delay time Symbol fmax tPLH/tPHL tPLH/tPHL Count mode tPLH/tPHL Load mode tPLH/tPHL tPHL tPHL Setup time tsu Min 80 55 -- -- -- -- -- -- -- -- -- -- -- -- 5.5 8.0 7.5 2.5 Hold time Pulse width th tw 1.0 5.0 5.0 Typ 130 85 8.3 10.8 8.7 11.2 11.0 13.5 7.5 10.5 8.9 11.2 8.4 10.9 -- -- -- -- -- -- -- Max -- -- 12.8 16.3 13.6 17.1 17.2 20.7 12.3 15.8 13.6 17.1 13.2 16.7 -- -- -- -- -- -- -- Ta = -40 to 85C Min 70 50 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 6.5 9.5 9.0 2.5 1.0 5.0 5.0 Max -- -- 15.0 18.5 16.0 19.5 20.0 23.5 14.5 18.0 16.0 19.5 15.5 19.0 -- -- -- -- -- -- -- ns ns Unit MHz ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CLK CLK CLK ENT CLR CLR Q Carry Carry Carry Q Carry FROM (Input) TO (Output)
ns
Data before CLK LOAD before CLK ENT, ENP before CLK CLR inactive before CLK CLK H or L CLR L
Rev.4.00 Jun. 04, 2004 page 8 of 15
HD74LV161A
Switching Characteristics (cont)
VCC = 5.0 0.5 V Ta = 25C Item Maximum clock frequency Propagation delay time Symbol fmax tPLH/tPHL tPLH/tPHL Count mode tPLH/tPHL Load mode tPLH/tPHL tPHL tPHL Setup time tsu Min 135 95 -- -- -- -- -- -- -- -- -- -- -- -- 4.5 5.0 5.0 1.5 Hold time Pulse width th tw 1.0 5.0 5.0 Typ 185 125 4.9 8.7 4.9 6.4 6.2 7.7 4.9 6.4 5.5 7.0 5.0 6.5 -- -- -- -- -- -- -- Max -- -- 8.1 10.1 8.1 10.1 10.3 12.3 8.1 10.1 9.0 11.0 8.6 10.6 -- -- -- -- -- -- -- Ta = -40 to 85C Min 115 85 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 4.5 6.0 6.0 1.5 1.0 5.0 5.0 Max -- -- 9.5 11.5 9.5 11.5 12.0 14.0 9.5 11.5 10.5 12.5 10.0 12.0 -- -- -- -- -- -- -- ns ns Unit MHz ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CLK CLK CLK ENT CLR CLR Q Carry Carry Carry Q Carry FROM (Input) TO (Output)
ns
Data before CLK LOAD before CLK ENT, ENP before CLK CLR inactive before CLK CLK H or L CLR L
Operating Characteristics
CL = 50 pF Item Power dissipation capacitance Symbol CPD VCC (V) 3.3 5.0 Ta = 25C Min Typ -- -- 17.0 20.4 Max -- -- Unit pF Test Conditions f = 10 MHz
Rev.4.00 Jun. 04, 2004 page 9 of 15
HD74LV161A
Noise Characteristics
CL = 50 pF Ta = 25C Item Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL Quiet output, minimum dynamic VOH High-level dynamic input voltage Low-level dynamic input voltage Symbol VOL (P) VOL (V) VOH (V) VIH (D) VIL (D) VCC (V) 3.3 3.3 3.3 3.3 3.3 Min -- -- -- 2.31 -- Typ 0.3 -0.3 3.0 -- -- Max 0.8 -0.8 -- -- 0.99 Unit V V V V V Test Conditions
Test Circuit
Measurement point
CL*
Note:
1. CL includes the probe and jig capacitance.
Rev.4.00 Jun. 04, 2004 page 10 of 15
HD74LV161A
Waveforms
Waveform - 1 Count mode twH twL VCC CLK 50%VCC 50%VCC GND
VOH Q, CARRY 50%VCC 50%VCC VOL tpLH tpHL
Waveform - 2 Preset mode VCC LOAD 50%VCC 50%VCC GND tsu th tsu th
A~D tsu th
50%VCC
VCC CLK 50%VCC 50%VCC GND t tpLH, pHL VOH Q, CARRY 50%VCC VOL
Rev.4.00 Jun. 04, 2004 page 11 of 15
HD74LV161A
Waveform - 3 Count enable mode VCC ENP ENT 50%VCC 50%VCC GND tsu th tsu th VCC CK 50%VCC 50%VCC GND VOH Q VOL Waveform - 4 Clear mode VCC CLR 50%VCC GND twL VCC CLK 50%VCC GND tsu VOH Q, CARRY tpHL 50%VCC VOL
Rev.4.00 Jun. 04, 2004 page 12 of 15
HD74LV161A
Waveform - 5
Cascade mode (Set to maximum count number)
VCC ENT 50%VCC 50%VCC GND
VOH CARRY 50%VCC 50%VCC VOL tpLH tpHL
Note: 1. Input waveform: PRR 1 MHz, Zo = 50 , t r 3 ns, t f 3 ns
Application
Cascade circuitry
H: COUNT L: DISABLE
INPUTS
INPUTS
INPUTS
LD A ENP
B
C
D
LD A ENP
B
C
D
LD A ENP
B
C
D
H: COUNT L: DISABLE
ENT CK
CARRY
ENT CK
CARRY
ENT CK
CARRY
to next stages
CLR QA QB QC QD
CLR QA QB QC QD
CLR QA QB QC QD
OUTPUT CLR CLK
OUTPUT
OUTPUT
Rev.4.00 Jun. 04, 2004 page 13 of 15
HD74LV161A
Package Dimensions
As of January, 2003
10.06 10.5 Max 16 9
Unit: mm
1
*0.20 0.05
8
0.80 Max
5.5
0.20 7.80 + 0.30 -
2.20 Max
1.15
1.27
0.10 0.10
0 - 8
0.70 0.20
*0.40 0.06
0.15
0.12 M
Package Code JEDEC JEITA Mass (reference value) FP-16DAV -- Conforms 0.24 g
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
9.9 10.3 Max 16 9
1 1.27 0.635 Max
8
0.11 0.14 + 0.04 - 1.75 Max
3.95
*0.20 0.05
0.10 6.10 + 0.30 -
1.08
0 - 8
0.67 0.60 + 0.20 -
*0.40 0.06
0.15 0.25 M
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
FP-16DNV Conforms Conforms 0.15 g
Rev.4.00 Jun. 04, 2004 page 14 of 15
HD74LV161A
As of January, 2003
Unit: mm
5.00 5.30 Max 16 9
1
*0.20 0.05
8 0.65 0.13 M 0.65 Max 6.40 0.20 0 - 8 0.50 0.10 1.0
4.40
*0.15 0.05
1.10 Max
0.10
0.07 +0.03 -0.04
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
TTP-16DAV -- -- 0.05 g
Rev.4.00 Jun. 04, 2004 page 15 of 15
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
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